The present invention relates to scan chain testing of electrical systems, in general, and more particularly, to a method and system of modifying data in functional latches of a logic unit during scan chain testing thereof to verify a test case failure of a suspected cell.
Today's electrical systems are generally embedded in very large scale integrated (VLSI) circuits which contain hundreds of thousands if not millions of electrical cells. Usually, these cells are grouped into functional units which may include both combinational logic and sequential logic comprised of clocked memory elements referred to as functional latches. After fabrication, each VLSI circuit is tested to check the functionality of its logic circuits and the interconnections thereof. In order to expedite this process, the VLSI circuits are fabricated with test circuits, which may be in the form of JTAG scan chains, for example. JTAG scan chain circuits are constructed and operated by a test access process (TAP) controller in accordance with the IEEE standard 1149.1.
Typically, the latches of a functional unit within a VLSI circuit are interfaced to corresponding scan latches in a boundary scan chain as illustrated by way of example in the block diagram schematic of FIG. 1. More specifically, scan latches SL1, . . . , SLN of a test scan chain are controlled by the TAP controller 10 to test the functional logic unit 12 shown within the dashed lines. Each scan latch SL1, . . . , SLN is coupled to a corresponding functional latch FL1, . . . , FLN in unit 12 by signal lines S1, . . . , SN, respectively. Test bit patterns are supplied by the TAP controller 10 to the scan latches SL1, . . . , SLN over a serial bus 14 which is daisy chained among the serial in (SI) and serial out (SO) ports of the latches SL1, . . . , SLN. The serial bus 14 begins and ends in the TAP controller 10 so that resultant test data may be read from the scan latches SL1, . . . , SLN to the TAP controller 10 thereover.
In operation, the TAP controller 10 may be operated by standardized JTAG bus signals TCK, TDI, TDO, TRST, and TMS to control the flow of test and resultant bit pattern date over the serial bus 14 through control signals comprising Shift, Update and Write provided to the scan latches SL1, . . . , SLN over a parallel bus 16. The functional logic unit 12 may be synchronized in operation by a master system clock (MCK), for example. Accordingly, the TAP controller 10 may introduce a test bit pattern to and read the resultant bit pattern from the functional latches FL1, . . . , FLN of unit 12 through the chain of scan latches SL1, . . . , SLN via respective signal lines S1, . . . , SN utilizing the clock MCK and control signals of bus 16. From the resultant bit pattern, the TAP controller 10 in cooperation with a Debug unit 18 may determine a failure in the functionality and/or circuit interconnection of the unit 12. However, as a result of the functional interdependency of the cells of the unit 12, it may not be possible to verify the particular cell or cells that have failed without further complex processing.
Accordingly, from this perspective, it is important and desirable to have a method and system of scan chain testing which may permit verifying the particular cell or cells causing the detected failure in a functional unit of a VLSI circuit. The present invention provides for such a method and system.